Junjie Lu , Student Member , IEEE , Steven Young , Student Member , IEEE , Itamar Arel , Senior Member

An analog implementation of a deep machinelearning system for ef cient feature extraction is presented in this work. It features online unsupervised trainability and non-volatile oating-gate analog storage. It utilizes a massively parallel recon gurable current-mode analog architecture to realize ef cient computation, and leverages algorithm-level feedback to provide robustness to circuit imperfections in analog signal processing. A 3-layer, 7-node analog deep machine-learning engine was fabricated in a 0.13 μm standard CMOS process, occupying 0.36 mm2 active area. At a processing speed of 8300 input vectors per second, it consumes 11.4 μW from the 3 V supply, achieving 1×1012 operation per second per Watt of peak energy ef ciency. Measurement demonstrates real-time cluster analysis, and feature extraction for pattern recognition with 8-fold dimension reduction with an accuracy comparable to the oating-point software simulation baseline.